Buried power rails and backside power distribution for nanometer-scale IC design

Дарья Игоревна Рыжова,Иван Владимирович Павлов,Иван Сергеевич Асапов

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Эта статья является препринтом и не была отрецензирована.
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Buried power rails and backside power distribution for nanometer-scale IC design

Д. И. Рыжова,

И. В. Павлов,

И. С. Асапов

2025-01-12

https://doi.org/10.24108/preprints-3113340

Buried power rails (BPR) and backside power delivery networks (BSPDN) technologies are promising tools for reducing the size of CMOS circuits. They provide significant improvements in many system-level parameters, such as IR-drop and power losses are reduced by more than 2 times, and by more than 4 times when using a buried power rail made of ruthenium, and the delay on critical paths and the overall area of the circuit are also significantly reduced. However, to fully realize the potential of this technology, a number of process and architectural issues need to be addressed. In this paper, the authors discuss the prospects and challenges associated with the implementation of buried power rails and backside power distribution networks. The physical characteristics of the semiconductor devices were also selected for process simulation in the Synopsys Sentaurus TCAD environment, as well as for physical synthesis in commercial CAD systems and open-source software. The developed models and methods will be included in the open flow for CMOS integrated circuits design with a 15 nm process and below.

Ссылка для цитирования:

Рыжова Д. И., Павлов И. В., Асапов И. С. 2025. Buried power rails and backside power distribution for nanometer-scale IC design. PREPRINTS.RU. https://doi.org/10.24108/preprints-3113340

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